20+ câu trắc nghiệm Thiết kế hệ thống số dùng HDL có đáp án

Raising edges of the clock will appear at times 5, 15, 25, 35, …

Raising edges of the clock will appear at times 5, 10, 15, 20, …

None of the above

Raising edges of the clock will appear at times 10, 20, 30, 40, …

The synthesis tool will give an error

A pure combinational circuit using NOT, NOR, and XNOR logic gates will be implemented

A latch with enable signal c will be generated for the output

A 2-to-1 multiplexer will be generated

It cannot be determined exactly how many times the value of ‘x’ will be printed

The simulation will print the current value of ‘x’ 15-times

The simulation will print the current value of ‘x’ 13-times

The simulation will always display 15 as the value of ‘x’

The synthesize system will generate a wire for result

A combinational circuit will be generated

None of the above

A sequential circuit with a storage element for result will be generated

None of these

A 4-bit parallel-in parallel-out register

A 4-bit shift register

Four D flip-flops all fed with the data “din”

110x

1100

xxxx

None of the above

All the variables will get the value previously stored in “z”

Shift the values stored in the three variables

All the variables will get the value previously stored in “y”

All the variables will get the value previously stored in “x”

It specifies that the unit of delay is 5 nanoseconds

It pauses execution of the statements that follow after time 5

It schedules the execution of the next statement at time 5

It specifies a delay of 5 time units before executing the next statement

None of these

It can be used to iterate a block indefinitely

It can be used to repeat execution of the block exactly two times

It can be used to iterate a block until a specified condition is true

6’b111000

6’b011000

None of the above

6’b111111

D = C + 1;

B[3:0] = D[4:1] + 1;

D = A + B;

C = A + D;

00100110

00111110

01111110

None of these