Which of the following is true for the module given below?
module mydesign (a,b,c);
input
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Which of the following is true for the module given below? module mydesign (a,b,c); input c; output reg a, b; always @(c) begin if (c == 1’b0) begin b <= ~a; a <= ~(c | b); end else if (c == 1’b1) a <= ~(b ^ c); end endmodule (multiple choices)
The synthesis tool will give an error
A pure combinational circuit using NOT, NOR, and XNOR logic gates will be implemented
A latch with enable signal c will be generated for the output