Which of the following is true for the following module?
module mydesign (a,b);
input [1:0]
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Which of the following is true for the following module? module mydesign (a,b); input [1:0] b; output reg a; always @(b) begin if (b==2'b00) a = 1'b0; else if (b==2'b11) a = 1'b0; else a = 1'b1; end end module
A latch will be generated for the output "a"
The synthesis tool will give an error
A combinational circuit implementing an AND function will be generated
A combinational circuit implementing a XOR function will be generated