What will the following code segment generate on synthesis, assuming that the four variables data0, data1, data2 and data3 map into four latches/flip-flops? always @(posedge clock) begin data

What will the following code segment generate on synthesis, assuming that the four variables data0, data1, data2 and data3 map into four latches/flip-flops?

always @(posedge clock)

begin

data3 = din;

data2 = data3;

data1 = data2;

data0 = data1;

end