20+ câu trắc nghiệm Thiết kế hệ thống số dùng HDL có đáp án

If “clk” and “clear” are two inputs of a counter module, which of the following event expressions must be used if we want to implement asynchronous clear (assuming “clear” is active low, acti

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If “clk” and “clear” are two inputs of a counter module, which of the following event expressions must be used if we want to implement asynchronous clear (assuming “clear” is active low, active high edge of “clk” signal is used for counting, and single “always” block is used for the implementation)?

always @(negedge clear)

always @(posedge clk or negedge clear)

always @(posedge clk)

None of these

Giải thích

Chọn đáp án B.