Consider the following Verilog module. module guess (data, cond, result); input [7:0] data; input [1:0] cond; output reg result; always @(data) begin if (cond == 2’b00) result = |data; else r13/21Consider the following Verilog module. module guess (data, cond, result); input [7:0] data; input [1:0] cond; output reg result; always @(data) begin if (cond == 2’b00) result = |data; else result = ~^data; end endmodule Which of the following are true when the module is synthesized? (multiple choices)The synthesize system will generate a wire for resultA combinational circuit will be generatedNone of the aboveA sequential circuit with a storage element for result will be generatedGiải thíchChọn đáp án B.